Generating Telecommunication Architectures in the DSP Station Environment

The C Telecommunication library within DSP Station CAD framework is provided only for simulation purpose. These Telecom C primitives do only execute the corresponding algorithms without any hardware implementation concepts. Consequently, the designer is confronted to a dead end when trying to generate the final synthesisable telecom design from his (or her) C telecom processor description. The GENCELL project (EUREKA project in collaboration with Mentor Graphics) aims to propose a novel design flow and its supporting tool to overcome this important restriction. Our design flow starts from high level requirements and constraints such as implementation style, data size, error recovering, information to the final synthesisable VHDL telecom architecture. These constraints are derived from the simulation results and from the parameters of the C units selected from the telecom design library. This method is mainly based on a repository of highly flexible and synthesisable VHDL cells dedicated to telecom applications and a configurable expert library management system. The Module Manager is an expert system able to select the most appropriate telecom cells according to the designer's requirements and to provide all the necessary information to drive the Mistral2 synthesis process in order to generate our specific low-power target architecture. A first application implements a telecommunication transmitter including source and channel encoders as well as framing devices.